The control of memory bit lines, which are used to transfer data into and out of memory cells, is subject to precise timing constraints. For instance, a typical memory read operation includes driving bit lines by connecting them to the corresponding memory cells, amplifying the bit line voltages (e.g., with a sense amplifier), and precharging the bit lines in preparation for subsequent operations. Each of these stages must be triggered in sequence. If a particular stage is initiated too soon (e.g., the precharge stage is commenced before sense amplification has completed), data could be corrupted.
A typical memory write operation has similar constraints. The operation often includes writing new data to bit lines using write drivers, connecting the bit lines to the corresponding memory cells, and precharging the bit lines in preparation for subsequent operations. As with read operations, the stages of a memory write must be triggered in the correct sequence. Beginning one stage before the previous stage has completed may result in data corruption and reduction of overall system integrity.
Delay chains are often used to enforce the timing sequences described above. These chains are usually tuned to a representative group of bit lines, and are designed to introduce appropriate amounts of delay for that group. Unfortunately, timing conditions often vary across different areas of a chip, due to process, voltage, and temperature (“PVT”) variation. In addition, parasitic and process effects such as coupling, length of diffusion (“LOD”) stress, and lateral diffusion make reliable timing control even more difficult.
In order to account for variations such as those listed above, bit line memory delays are often allocated liberally. That is, designers will often choose one set of delays that will work for all bit lines and apply them across the entire memory. Although this approach is relatively simple and robust, it leads to excessive delay in many areas of a chip. Since memory bit lines are accessed and driven by a variety of different circuits, and since they are often used on a recurring basis, these inefficiencies can lead to a significant performance loss.
In view of the foregoing, it would be desirable to provide circuitry and methods that vary the delay of each stage of a memory bit line operation across different areas of a chip. In addition, it would be desirable to vary this delay in a way that optimizes the speed of each operation, without the use of careful hand tuning to compensate for PVT or parasitic effects.